View STV0116_1793216.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STV0116 pal/ntsc digital encoder may 1996 advance data 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 ycrcb3 ycrcb2 ycrcb1 ycrcb0 test8 testauto ys i ref1 c cvbs v dda v ssa r i ref2 g b test7 test6 test5 test4 h27 test3 test2 test1 test0 v ssc odd/even vcs ycrcb7 ycrcb6 ycrcb5 ycrcb4 v ddc nreset sda scl ri gi bi fb testscan h6osd v ssp v ddp 0116-01.eps pin connections plcc44 (plastic chip carrier) order code : STV0116 . both 625 & 525 lines multiplexed 8 bit digital input according to ccir 601-2 and rec 656 . ntsc m, pal m, pal b, d, g, h, i, pal n (argentina) programmable output . composite or line synchronism out- put . cvbs, y, c analog outputs through 9 bit dacs . rgb analog outputs through 8 bit dacs . osd insertion with clut and 6.75mhz output clock reference . true 27mhz modulator . true ntsc encoding with i, q axis . oversampling to 27mhz for easy output filtering . odd/even synchronism input/output . on chip test pattern generator . i 2 c bus controlled . easy configuration to any stand- ard with one register loading this is advance information on a new product now in development or undergoing evaluation. details are subject to change without no tice. description the STV0116 converts the digital output of a video mpeg decoder into a standard analog base band ntsc/pal signal, with a modulated subcarrier. both composite and svhs format video signals are simultaneously delivered to 3 analog outputs. the STV0116 includes additionnally three analog rgb outputs to be used for the scart plug. 1/22
pin description pin n symbol type function 23 h27 i 27mhz input clock reference. low/high ratio : 50%. fall and rise time : 5ns max. the rising edge is the reference for hold and setup time of all inputs. the duration of high/low level is in accordance with rec656 (18.5ns 3ns with less than 3ns of jitter). 7 odd/even i/o odd/even frame input (slave mode by odd/even), output (master mode or slave mode by eav). the synchronism reference is the rising edge of h27. default polarity : odd field = low level, even field = high level. 5 nreset i the hard reset is active low. it has priority on software reset. fall and rise time of hard nreset < 20ns. hold time of hard nreset > 80ns. no synchronism of hard nreset is necessary. nreset imposes default states. 3 scl i serial interface with microcontroller. spread of frequency : 0 to 400kbit/s. level 0 > 200ns. trigger pads to ensure a low frequency input. maximum capacitance for each bus line (400pf). chip address (hex) : b0 (write mode), b1 (read mode). 4 sda i/o 9 to 16 ycrcb [7:0] i time multiplexed 4:2:2 luminance and color difference input as defined in ccir rec 601_2 and rec 656 (ttl levels inputs). 525 lines/60hz or 625 lines/50hz. timing (rec 656 part ii). a line length is 1716 or 1728 periods of 27mhz for 525 or 625 line systems respectively. 2 - 1 - 44 ri, gi, bi i osd serial inputs. osd_pixel minimum width is 148ns (i.e. 6.75mhz). ri, gi, bi transcoded to y, cr, cb according to clut (8 colors among 262144). clut tint programmable 43 fb i fast blanking is minimum 1 osd_pixel large. fb synchronous to h27. osd active when fb is high. 41 h6osd o 6.75mhz clock output for the reference of an osd input signal. 8 vcs o composite synchronization or horizontal line synchronization output. polarity (default : positive). the synchronism reference is the rising edge of h27. 37 i ref1 i reference current source of the triple 9 bit dac for cvbs, ys and c. for a reference load of 1.8k ? : 1.7 < i ref1 (ma) < 2.1. 35 cvbs o current analog video composite output. 38 ys o current analog luminance output with composite synchronization, svhs compatible. 36 c o current analog chrominance output, svhs compatible. 32 - 30 - 29 r, g, b o current analog outputs synchrone with cvbs. 31 i ref2 i reference current source of the triple 8 bit dac for r, g, b. for a reference load of 1.8k ? : 1.7 < i ref2 (ma) < 2.1. 40 - 22 v ssp -v ddp 0v-5v supply for pads. 24 - 6 v ssc -v ddc 0v-5v supply for core. 33 - 34 v ssa -v dda 0v-5v supply for dacs. 0116-01.tbl STV0116 2/22
bus bus bus 2 1 44 43 ri gi bi fb clut cb y cr 6 3 int color bars bus 8 6mhz cb cr u/q v/i matrix 8 8 cr cb y demux 8 8 int 27mhz delay int 27mhz int 27mhz 1.8mhz 1.8mhz 8 8 27mhz int modulator c 9 bit d/a 9 9 9 9 bit d/a 9 bit d/a 38 35 36 9 8 bit d/a 8 bit d/a 8 bit d/a 29 30 32 8 8 8 cr cb r g b y rgb matrix 78 vcs d/a ref sync gen d/a ref bus y/cr/cb i c bus decoder 3 4 sda scl reset test 12 nreset test 23 clock gen h27 sub-carrier synthesizer odd/even r g b ys cvbs c STV0116 pins 9 to 16 5 pins 18 to 21 25 to 28 37 31 6 6 2 v dd 1.3mhz/ 1.8mhz 0.5mhz 41 h6osd v dd bus v/i u/q delay delay delay int : interpolator 0116-02.eps block diagram STV0116 3/22
absolute maximum ratings symbol parameter value unit v dd supply voltage 7 v v in digital inputs v dd + 0.3 v v out digital and analog outputs 0, v dd v t oper operating temperature 0, +70 o c t stg storage temperature -20, +150 o c 0116-02.tbl electrical characteristics symbol parameter test conditions min. typ. max. unit dc (v dda =v ddp =v ddc = 5v, t amb = 0 to 70 o c, unless otherwise specified) supply v dda analog supply voltage 4.75 5 5.25 v i dda analog supply current i ref1 =i ref2 = 3ma r l = 400 ? 30 ma v ddp output buffer supply voltage 4.75 5 5.25 v i ddp output buffer supply current autotest mode 30 ma v ddc core supply voltage 4.75 5 5.25 v i ddc core supply current autotest mode 20 ma digital inputs v l input voltage low (sda, scl) -0.50 1.50 v v h input voltage high (sda, scl) 3 7 v v il input voltage low (any others are ttl compatible) -0.50 0.80 v v ih input voltage high (any others are ttl compatible) 2v dd + 0.5 v i l input leakage current v ilmin or v ihmax 10 a c l input capacitance (all inputs) 10 pf digital outputs v ol output voltage low i ol = 1ma v ss 0.60 v v oh output voltage high i oh = -1ma 2.40 v dd v dacs res1 resolution (ys, c, cvbs) 9 bits res2 resolution (r, g, b) 8 bits ile integral linearity error i ref = 3ma, v dda = 5v, r l = 400 ? 2 lsb dle differential linearity error i ref = 3ma, v dda = 5v, r l = 400 ? 1 lsb i g current gain 2 g e gain error 3 % 0116-04.tbl STV0116 4/22
symbol parameter test conditions min. typ. max. unit ac (v dda =v ddp =v ddc = 5v, t amb = 0 to 70 o c, c l = 20pf, unless otherwise specified) digital inputs t s input data set-up time 5 ns t h input data hold time 10 ns digital outputs t d output delay time c l = 10pf 29 ns ph0 output phase of h6osd after reset h27 fmi frequency of scl 2 mhz clock input t c clock cycle time 27 mhz t d clock duty factor 50 % t r clock rise time 5ns t f clock fall time 5ns dac output t dh output delay time 32 lsb max step 9 bit dac 16 lsb max step 8 bit dac i ref = 3ma, r l = 400 ? , c l = 10pf 29 ns 0116-04.tbl electrical characteristics (continued) v dd /2 v dd /2 t d t s t h v dd /2 h27 digital output digital input nreset h6osd 0.1v step 0.1v step v step t dh dac output 0116-21.eps figure 1 STV0116 5/22
circuit description the STV0116 can operate either in master mode or in slave mode receiving a vertical parity synchro- nism signal from mpeg ic. an i 2 c bus allows to control the main functions : - selection of the standard, - synchronisation mode and polarity, - color killing, - reset of the synchronism and oscillator, - test mode, - by-pass of the chroma filters, - sub-carrier phase and frequency adjustment, - osd clut. pixel input format the digital input is a time multiplexed ycbcr 8 bit stream. the samples represent a successionof cb/y/cr/y component values and are latched on the rising edge of h27 (27mhz clock). this input is fully compatible with sgs-thomson mpeg decoder ic?s outputs. video timing the STV0116 outputs interlaced video to conform to the ntsc or pal timing specifications. non standard line counts in pal or ntsc modes are not supported. the 8 field (for pal) and 4 field (for ntsc) burst sequences are internally generated, using the 27mhz clock as reference. rise and fall times of sync, blanking interval, and the burst envelope are internally controlled accord- ing to the composite video specification (see fig- ures 6 and 7). only lines 1 to 9, 264 to 272 for 525 and 624 to 5, 311 to 318 for 625 lines system respectively are blanked. the others can be used for data encoding. master mode after a software reset, the sync generator starts counting 27mhz clock pulses and provides a com- plete composite sync pulse sequence of 4 fields to the ntsc encoder. for pal, the combination with the odd/even line sequence gives the 8 field sequence for the color burst insertion. at the end of a sequence the counter is automatically reset and a new sequence can start. in the same time an odd/even frame pulse is output to control the mpeg decoder. slave mode after a software reset, the sync counter waits for the falling edge of the odd/even pulse sent to the odd/even pin selected as an input. then a se- quence identical to the one in master mode can start and is reset by the next falling edge of the field pulse (see figure 2). if no odd/even pulse is present after a full 3 frames sequence, the ic can either regenerate itself the next sequencesin ?free running? using the 27mhz clock, or switch on the internal test bar pattern, or blank the outputs, after reading status register. alternatively the STV0116 can be set to extract the synchronization directly from the y/cr/cb input data sequence (see figure 3). these different modes are selectable by the i 2 c bus. chrominance encoding the demultiplexed cr, cb samples feed a chroma i/q matrix for ntsc and a u/v matrix for pal. the u/v or i/q chroma signals are then band limited according to the ccir 624 recommendations and interpolated at a 27mhz pixel rate. this process makes easier the filtering for the d/a convertion and allows a more accurate encoding. a discrete time oscillator, using a 22 bit phase accumulator, generates the color sub-carrier. this signal feeds a quadrature modulator which modu- lates the baseband chroma signals. the phase and the frequency of the sub-carrier can be adjusted if needed or reset by software. luminance processing the demuxed y samples are band limited and interpolated at 27mhz samples rate. then a gain and offset compensation is applied to the luma signal before inserting the synchronism pulses. the interpolation filter compensates for the sinx/x attenuation provided by the d/a convertion, and greatly simplifies the output filtering. a delay is inserted in the luma path to transmit correctly picture transition. cvbs and svhs outputs each digital signal drives a 9 bit d/a converter operating at 27mhz. the outputs are current sources and are propor- tional to the current reference value. for 3ma reference current and 400 ? load, the levels are such that a pnp emitter follower is enough to drive the scart plug (1v from sync tip to white level). the integrated over sampling filters make the ex- ternal antiliasing low pass filter simpler. STV0116 6/22
reset procedure a hard reset is performed by groundingthe reset pin. this will set the ic in pal bdghi and slave mode. the ?software reset? configure the ic according to the configuration fixed by register 0 (that isn?t re- seted itself). the sync generator is then ready for a new sequence. this will be initialized either by the next clock pulse in master mode, or by the next field pulse in slave mode. r, g, b outputs after demux, cr/cb data feed a 4 times interpola- tion filter at 27mhz sample rate. then the chroma base-band signal is band limited at 1.8mhz and matrixed with y. three 8 bit d/a converters gener- ate r, g, b outputs at 27mhz. h6osd output this 6.75mhz clock signal is intended to trig the osd input data. it is synchronous with the h27 clock reference. r, g, b, fb osd inputs these are logic inputs for osd insertion. fb (fast blanking) is used to switch from the main video input to the rgb inputs. fb and rgb inputs must be locked to the h27 clock. they are latched on the rising edge of 6.75mhz clock signal. the rgb inputs allow 8 color combinations. the internal clut (color look up table) affects for each of these 8 values a color chosen among 643 preset for y, cr, cb components. as clut performs the matrixing into y, cr and cb, the resulting signals take benefit of the oversampling filters in the main path. additionally the y signal is interpolated. in- serted osd rate is 6.75mbit/s. signal quality detector it is active if the timing reference synchronization data of the input data stream is present. by use of hamming decoding in video y/cr/cb (eav, sav), the ic generates a bit (hok). this bit indicates multiple errors of the hamming decoding. it can be read by the microcontroller. t0 + 625 (525) input input input h27 odd/even ycrcb tpi t0 yy cb cb y cb y cb y cb 1728 (1716) . h27 is the reference for odd/even and ycrcb timing. odd/even is the reference for video input and output. active pixels are read from ycrcb data. first active pixels of first full line is read from ycrcb at tpi = t0 + 6 ? 1728t + 264t (pal bgihdn) t0 + 7 ? 1716t + 244t (pal m & ntsc m) 0116-04.eps figure 2 : slave 1 (slave by odd/even) 1728 (1716) input input h27 ycrcb y cb b6 00 ff 00 t0 tpi cb y cb y cb cb . t0 + 625 (525) timing reference synchronization 0116-05.eps h27 is the reference for ycrcb timing. ycrcb is the reference for video input and output. first active pixels of first full line is read from ycrcb at tpi = t0 + 6 ? 1728t + 264t (pal bgihdn) t0 + 7 ? 1716t + 244t (pal m & ntsc m) figure 3 : slave 2 (slave by eav, end of active video, taken on ycrcb) circuit description (continued) master/slave functionality t = 1 period of h27. duration of active line is 1440t. STV0116 7/22
output output input vcs odd/even ycrcb input h27 80 10 cb t0 tpi y 0116-06.eps h27 is the reference for odd/even, vcsand ycrcb timing. falling edge is the reference if odd/even is active low. first active pixels of first full line is read from ycrcb at tpi = t0 + 6 ? 1728t + 264t +2 (pal bgihdn) t0 + 7 ? 1716t + 244t +2 (pal m & ntsc m) figure 4 : master mode h27 input t/2 t/2 5ns 3ns jitter v dd 0.9v dd 0.1v dd v dd /2 0116-07.eps figure 5 : h27 input maximum acceptance t0 h27 input vcs output tpvcs odd/even input cvbs output tpcvbs 9t 0116-08.eps pal bgihdn tpvcs = 772 ? t+n ? tline tpcvbs = 778 ? t+ n ? t line pal m & ntsc m tpvcs = 758 ? t+n ? tline tpcvbs = 764 ? t+ n ? tline figure 6 : logic and analog synchronisms freerun and slave mode if freerun is allowed and the vertical synchronism is lost, all the video signals are generated with the picture sampled on ycrcb. vcs is still available. if freerun is not allowed vcs is stopped and ys, c, cvbs, r, g, b are at black level. synchronization signals t = 37.037ns = 1 period of h27 (27mhz). t0 h27 input vcs output tpvcs ycrcb input cvbs output tpcvbs ff 00 00 b6 80 timing reference synchronization 9t 0116-09.eps pal bgihdn tpvcs = 791 ? t+ n ? tline tpcvbs = 797 ? t+n ? t line pal m & ntsc m tpvcs = 785 ? t+ n ? tline tpcvbs = 791 ? t+n ? tline figure 7 : logic and analog synchronisms (slave by eav synchro only) magenta ycrcb or osd cvbs, c, ys, r, g or b ~ 60t green transition 0116-22.eps figure 8 : ycrcb and osd delay to analog output STV0116 8/22
370 323 293 247 217 170 400 140 20 ire 20 ire 7.5 ire 40 ire 100 ire 34 ire 120 8 48 3.58mhz color burst (9 cycles) sync level blank level black level white level white yellow 119 cyan 171 green 159 magenta 155 red 169 blue 119 black 120 0116-10.eps figure 9 : m composite ntsc output (100% saturation, 100% amplitude colour bars) 375 324 292 242 210 159 407 43 ire 100 ire 33 ire 127 8 4.43mhz color burst (10 cycles) sync level black/blank level 127 white level 21.5 ire 64 21.5 ire 33 ire white yellow 128 cyan 181 green 171 magenta 169 red 182 blue 129 black 0116-11.eps figure 10 : composite pal bgdhin output (100% saturation, 100% amplitude bars) STV0116 9/22
370 323 293 247 217 170 400 33 ire 40 ire 100 ire 34 ire 120 8 3.58mhz color burst (9 cycles) sync level black level white level 20 ire 20 ire 64 white yellow 119 cyan 167 green 159 magenta 158 red 169 blue 119 blank level 7.5 ire 140 120 black 0116-12.eps figure 11 : composite pal m output (100% saturation, 100% amplitude bars) STV0116 10/22
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 (db) 014 24 6 81012 x10 6 (hz) 0116-13.eps figure 12 : luma filter -9 -8 -7 -6 -5 -4 -3 -2 -1 0 (db) 07 12 3 45 6 x10 6 (hz) 1 0116-18.eps figure 12a : luma filter 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 (db) 014 24 6 81012 x10 6 (hz) 0116-14.eps figure 13 : chroma q filter 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 (db) 9 8 7 6 5 4 3 2 x10 5 (hz) 1 0 0116-19.eps figure 13a : chroma q filter 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 (db) 014 24 6 81012 1.75mhz 1.25mhz x10 6 (hz) 0116-15.eps note : those filter curves include the sinx/x attenuation of dacs. figure 14 : chroma filters 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 (db) 3 2.8 2.6 2.4 2.2 2 1.8 1.6 x10 6 (hz) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.75mhz 1.25mhz 0116-20.eps figure 14a : chroma filters STV0116 11/22
i 2 c registers description the ic is controlledby an i 2 c bus and internal registers can be read or written by an external microcontroller. encoder addresses are : - write 10110000 (b0 hex). - read 10110001 (b1 hex). registers are organized as follows : reg 0 : sync mode selection, standard selection, sync polarity selection reg 1 : color killer, chroma filter selection, sync output selection reg 2, 3 : sync delay reg 4 to 9 : sub-carrier frequencies reg 10 to 17 : y clut for rigibi input encoding reg 18 to 25 : cr clut for rigibi input encoding reg 26 to 33 : cb clut for rigibi input encoding reg 34 : test (not to be used) reg 35 : status reg 36 to 38 : line forcing i 2 c format write mode (all registers except status) s slave address w a sub-address a data 0 a ... data n a p s start condition slave address 1011000 w = ?0? write flag a acknowledge, generated by slave (STV0116) when ok a = ?0? else ?1? sub-address sub-address register (content is made of one byte) data 0 first data byte data n continued data bytes (address is automatically incremented) and a?s p stop condition read mode (all registers) s slave address w ac sub-address n ac p then : s slave address r ac data n am data n+1 am p s start condition slave address 7 bit address for STV0116 : 1011000 w = ?0? write flag ac acknowledge, generated by slave (STV0116) when ok, ac = ?0? else ?1? r = ?1? read flag sub-address 8 bit sub-address register data n data byte of register n, sent by STV0116 data n+1 data byte of register n+1 (address automatically incremented) am acknowledge, generated by the microcontroller am = ?0? when acknowledge is ok else ?1? p stop condition (when last am = ?1?) STV0116 12/22
remarks writing of a register : registers 0, 1, ..., 34 can be loaded sequentially with only one start/stop condition followed by the sub-address of the first register desired. example : start followed by address b0 and sub-address 1 and then 3 bytes of data and stop : the cfg register will be loaded with the first byte and delay register will be loaded with the 2 others bytes. reading of a register : example 1 : reading of register 35 (status) : start followed by address b0 hex, ac = ?0?, then sub-address 35, ac = ?0? and stop. then start, address b1, ac = ?0? and then data of register 35, am = ?1? and stop condition. example 2 : reading of registers 0 to 3 : start followed by address b0 hex, ac = ?0?, and sub-address 0, ac = ?0? and stop. then start, address b1, ac = ?0? and then first byte of register 0, am = ?0?, second byte from register 1, am = ?0?, third byte of register 2, am = ?0?, fourth byte from register 3, am = ?1? and stop condition. scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 i 2 c slave address b0 ack by STV0116 lsb address start d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 data byte 2 data byte 3 data byte n stop scl sda data byte 1 d6 d7 ack by STV0116 ack by STV0116 ack by STV0116 ack by STV0116 ack by STV0116 0116-16.ai figure 15 : STV0116/i 2 c write operation scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 i 2 c slaveaddress b0 lsb address start scl sda r/w d7 d6 d5 d4 d3 d2 d1 d0 data byte n start d7 d6 d5 d4 d3 d2 d1 d0 stop data byte 1 i 2 c slaveaddress b1 stop ack by STV0116 ack by STV0116 ack by micro ack by STV0116 ack by micro 0116-17.eps figure 16 : STV0116/i 2 c read operation STV0116 13/22
registers mapping and description (*) default mode on hard nreset. (**) default mode on testauto. register 0 control (read/write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 register 0 std1 std0 sym1 sym0 sys1 sys0 mod1 mod0 std1 std0 standard selection (*) 0 0 pal bdghi 0 1 pal n argentina 1 0 ntsc m 1 1 pal m sym1 freerun (*) 0 disable 1 enable : free-run is active even if odd/even is incorrectly positionned (with a time constant of 3 consecutive lost frames) in slave mode. sym0 frame synchronization source in slave mode (*) 0 odd/even input 1 ycrcb (extraction of f from eav) sys1 synchro : vcs polarity (*) 0 positive 1 negative sys0 frame synchro : odd/even polarity (as input (slave) or as output (slave : synchro from eav or master)) (*) 0 synchro on odd/even falling edge 1 synchro on odd/even rising edge mod1 (*) 0 no reset 1 software reset mod0 (*) 0 slave (**) 1 master (freerun forced) note : software reset is automatically disabled at i 2 c stop condition. reset is active during 4 h27 periods. STV0116 14/22
registert 1 cfg (read/write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 register 1 hsnvcs rstddfs flt1 syncok coki - - - hsnvcs output signal selection on vcs (*) 0 composite synchro 1 horizontal synchro rstddfs reset of ddfs (direct digital frequency synthetizer) 0 to 1 transition generates a pulse reset for oscillator 0 flt1 chroma pass band filter (*) 1 1.3mhz, 0.45mhz for q only 0 1.8mhz syncok synchro availability in case of no free-run active (*) 0 synchro off 1 synchro available (if sym1 = 0) coki color kill (*) 0 color on 1 color suppressed on c and cvbs (on cvbs only in next release) note : four filters for encoding needs. luma passband filter (6.3mhz (bw = 5.75mhz with sinx/x d/a conversion)) chroma passband filter (1.3mhz/1.8mhz : u/v and i, 1.8mhz/0.45mhz : q, 1.8mhz : cr, cb for r, g, b encoding) (chroma bw becomes 1.2mhz/1.7mhz, 0.45mhz, 1.7mhz with sinx/x dac). register 2 delay_msb (read/write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 register 2 d10 d9 d8 d7 d6 d5 d4 d3 register 3 delay_lsb msb lsb d7 d6 d5 d4 d3 d2 d1 d0 read mode : register 3 d2 d1 d0 reg2, d4 reg2, d3 reg2, d2 reg2, d1 reg2, d0 write mode : register 3 d2 d1 d0 xx xx xx xx xx d[10:0] sample polynomial counter at 27mhz sample polynomial counter (1 + x 2 +x 11 ) value on which falling edge of f (odd/even signal) is detected on ycrcb (f is extracted from eav word) 1st byte : 21 (hex 15), 2nd byte : 128 (hex 80) for pal bdghin (625 lines) 1st byte : 201 (hex c9), 2nd byte : 128 (hex 80) for m (525 lines) sample polynomial counter value on which falling edge of odd/even is detected (*) 1st byte : 0, 2nd byte : 32 (hex 20) for pal bdghin (625 lines) 1st byte : 0, 2nd byte : 32 (hex 20) for m (525 lines) note : delay register should be loaded before control register for synchro on ycrcb cross table of sample polynomial counter is given cech.txt file. registers mapping and description (continued) STV0116 15/22
register increment for ddfs (digital frequency synthesizer) (read/write) msb lsb (see note) d7 d6 d5 d4 d3 d2 d1 d0 register 4 xx xx d21 d20 d19 d18 d17 d16 register 5 d15 d14 d13 d12 d11 d10 d9 d8 register 6 d7 d6 d5 d4 d3 d2 d1 d0 (*) reset value depends on standard chosen in register 0 x x 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 ntsc m f = 3.5795452mhz error = +0.2hz f th = 3579545 10hz x x 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 pal bghi f = 4.4336206mhz error = +1.85hz f th = 4433618.75 5hz x x 0 0 1 0 0 0 0 1 1 1 1 1 0 1 1 0 1 0 0 1 0 1 pal n f = 3.5820558mhz error = -0.45hz f th = 3582056.25 5hz x x 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 pal m f = 3.5756120mhz error = +0.51hz f th = 3575611.49 5hz note : 1 lsb = 6.43hz register phase offset for ddfs (digital frequency synthesizer) (read/write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 register 7 xx xx o21 o20 o19 o18 o17 o16 register 8 o15 o14 o13 o12 o11 o10 o9 o8 register 9 o7 o6 o5 o4 o3 o2 o1 o0 (*) reset value depends on standard chosen in register 0 registers mapping and description (continued) STV0116 16/22
register palety (read/write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 read mode : register 10 reg10,d5 reg10,d5 y75 y74 y73 y72 y71 y70 register 11 reg11,d5 reg11,d5 y65 y64 y63 y62 y61 y60 register 12 reg12,d5 reg12,d5 y55 y54 y53 y52 y51 y50 register 13 reg13,d5 reg13,d5 y45 y44 y43 y42 y41 y40 register 14 reg14,d5 reg14,d5 y35 y34 y33 y32 y31 y30 register 15 reg15,d5 reg15,d5 y25 y24 y23 y22 y21 y20 register 16 reg16,d5 reg16,d5 y15 y14 y13 y12 y11 y10 register 17 reg17,d5 reg17,d5 y05 y04 y03 y02 y01 y00 write mode : register 10 xx xx y75 y74 y73 y72 y71 y70 register 11 xx xx y65 y64 y63 y62 y61 y60 register 12 xx xx y55 y54 y53 y52 y51 y50 register 13 xx xx y45 y44 y43 y42 y41 y40 register 14 xx xx y35 y34 y33 y32 y31 y30 register 15 xx xx y25 y24 y23 y22 y21 y20 register 16 xx xx y15 y14 y13 y12 y11 y10 register 17 ntsc xx xx y05 y04 y03 y02 y01 y00 register 17 pal (to be loaded) xxxx000100 8 x 6 bit words for y component. default value : r0, b0, c0 y(hexa) color (100% white to black) 111 3b white y7x 110 28 yellow y6x 101 14 magenta y5x 100 10 red y4x 011 21 cyan y3x 010 1d green y2x 001 09 blue y1x 000 04 black y0x registers mapping and description (continued) STV0116 17/22
register paletcr (read/write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 read mode : register 18 reg18,d5 reg18,d5 cr75 cr74 cr73 cr72 cr71 cr70 register 19 reg19,d5 reg19,d5 cr65 cr64 cr63 cr62 cr61 cr60 register 20 reg20,d5 reg20,d5 cr55 cr54 cr53 cr52 cr51 cr50 register 21 reg21,d5 reg21,d5 cr45 cr44 cr43 cr42 cr41 cr40 register 22 reg22,d5 reg22,d5 cr35 cr34 cr33 cr32 cr31 cr30 register 23 reg23,d5 reg23,d5 cr25 cr24 cr23 cr22 cr21 cr20 register 24 reg24,d5 reg24,d5 cr15 cr14 cr13 cr12 cr11 cr10 register 25 reg25,d5 reg25,d5 cr05 cr04 cr03 cr02 cr01 cr00 write mode : register 18 xx xx cr75 cr74 cr73 cr72 cr71 cr70 register 19 xx xx cr65 cr64 cr63 cr62 cr61 cr60 register 20 xx xx cr55 cr54 cr53 cr52 cr51 cr50 register 21 xx xx cr45 cr44 cr43 cr42 cr41 cr40 register 22 xx xx cr35 cr34 cr33 cr32 cr31 cr30 register 23 xx xx cr25 cr24 cr23 cr22 cr21 cr20 register 24 xx xx cr15 cr14 cr13 cr12 cr11 cr10 register 25 xx xx cr05 cr04 cr03 cr02 cr01 cr00 8 x 6 bit words for cr component. default value : r0, b0, c0 cr(hexa) color (75% white to black) 111 20 white cr7x 110 23 yellow cr6x 101 31 magenta cr5x 100 35 red cr4x 011 0b cyan cr3x 010 0e green cr2x 001 1c blue cr1x 000 20 black cr0x registers mapping and description (continued) STV0116 18/22
register paletcb (read/write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 read mode : register 26 reg26,d5 reg26,d5 cb75 cb74 cb73 cb72 cb71 cb70 register 27 reg27,d5 reg27,d5 cb65 cb64 cb63 cb62 cb61 cb60 register 28 reg28,d5 reg28,d5 cb55 cb54 cb53 cb52 cb51 cb50 register 29 reg29,d5 reg29,d5 cb45 cb44 cb43 cb42 cb41 cb40 register 30 reg30,d5 reg30,d5 cb35 cb34 cb33 cb32 cb31 cb30 register 31 reg31,d5 reg31,d5 cb25 cb24 cb23 cb22 cb21 cb20 register 32 reg32,d5 reg32,d5 cb15 cb14 cb13 cb12 cb11 cb10 register 33 reg33,d5 reg33,d5 cb05 cb04 cb03 cb02 cb01 cb00 write mode : register 26 xx xx cb75 cb74 cb73 cb72 cb71 cb70 register 27 xx xx cb65 cb64 cb63 cb62 cb61 cb60 register 28 xx xx cb55 cb54 cb53 cb52 cb51 cb50 register 29 xx xx cb45 cb44 cb43 cb42 cb41 cb40 register 30 xx xx cb35 cb34 cb33 cb32 cb31 cb30 register 31 xx xx cb25 cb24 cb23 cb22 cb21 cb20 register 32 xx xx cb15 cb14 cb13 cb12 cb11 cb10 register 33 xx xx cb05 cb04 cb03 cb02 cb01 cb00 8 x 6 bit words for cb component. default value : r0, b0, c0 cb(hexa) color (75% white to black) 111 20 white cb7x 110 0b yellow cb6x 101 2e magenta cb5x 100 19 red cb4x 011 27 cyan cb3x 010 12 green cb2x 001 35 blue cb1x 000 20 black cb0x registers mapping and description (continued) STV0116 19/22
register 35 status (read) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 register 35 hok atfr std1 std0 sym1 sym0 sys1 sys0 hok hamming decoding of odd/even signal from ycrcb 0 multiple errors 1 0 or 1 error atfr frame synchronization flag 0 encoder not synchronized 1 in slave mode : encoder synchronized std1 std0 standard selection (*) 0 0 pal bdghi 0 1 pal n (argentina) 1 0 ntsc m 1 1 pal m sym1 freerun (*) 0 disable 1 enable : free-run is active in case of odd/even suppression (with a time constant of 3 consecutive lost of frame) and slave mode sym0 frame synchronization source in slave mode (*) 0 odd/even input 1 ycrcb (expraction of f from eav) sys1 synchro : vcs polarity (*) 0 positive 1 negative sys0 frame synchro : odd/even polarity (*) 0 synchro on odd/even falling edge 1 synchro on odd/even rising edge note : signal quality detector by use of hamming decoding on eav, sav in ycrcb input. register compression (read/write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 read mode : register 36 lf9 lf8 lf7 lf6 lf5 lf4 lf3 lf2 register 37 lf1 lf0 lc9 lc8 lc7 lc6 lc5 lc4 register 38 lc3 lc2 lc1 lc0 0000 write mode : register 36 lf9 lf8 lf7 lf6 lf5 lf4 lf3 lf2 register 37 lf1 lf0 lc9 lc8 lc7 lc6 lc5 lc4 register 38 lc3 lc2 lc1 lc0 xxxx it is used to compress on line fonctionnal patterns. ?lc? is the line number value* on which the polynomial line counter (1 + x 3 +x 10 ) is forced (when it occurs) with ?lf? value. (*) on reset ?lf? = 001, ?lc? = 000 (line counter never goes to 000 value) 1st byte : 00, 2nd byte : 40 hex, 3rd byte : 00 registers mapping and description (continued) STV0116 20/22
v ddp 4.7k ? v ddp 4.7k ? scl sda mcu 7 8 9 10 16 17 18 19 20 26 27 28 29 30 36 37 38 39 40 11 12 13 14 15 21 22 23 24 31 32 33 34 35 25 1 2 3 4 5 644434241 ntc ntc ntc ntc ri gi bi fb vcs ntc ntc ntc ntc ntc h27 v ssc v ssp 0.8k ? v ssa v ddc 100nf 10 f r81 odd/even y/cr/cb7 y/cr/cb6 y/cr/cb5 y/cr/cb4 y/cr/cb3 y/cr/cb2 y/cr/cb1 y/cr/cb0 mpeg decoder v ddp 100nf 10 f v dda 100nf 10 f 220pf v dda STV0116 ntc v dda v ddc v ddp : not to be conne cte d :5v :5v :5v 75 ? 390 ? 120 ? :v ssa (0v) h6osd i 2 c interface osd interface ccir 656 interface luminance processing 9 bit tridac synchronism processing chrominance processing o/e vcs :v ss (0v) = v ss p =v ssc hsync 8 bit tridac video output sta ge 75 ? 1.8k ? in out video output sta ge 75 ? in out video output sta ge 75 ? in out video output sta ge 75 ? in out video output sta ge 75 ? in out video output sta ge 75 ? in out in out vide o output stage nreset 0116-03.eps application diagram STV0116 21/22
pmplcc44.eps package mechanical data 44 pins - plastic chip carrier dimensions millimeters inches min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 plcc44.tbl information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without noti ce. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1996 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system confo rms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STV0116 22/22

▲Up To Search▲

Price & Availability of STV0116

	To Download STV0116 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .